----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    13:18:51 04/25/2012 
-- Design Name: 
-- Module Name:    anode_rotator - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity anode_rotator is
	Port (
			clk : in std_logic;
			update_pulse : in std_logic;
			anode : out std_logic_vector(3 downto 0)
		);
end anode_rotator;

architecture Behavioral of anode_rotator is

	signal data_current : std_logic_vector(3 downto 0) := "0111";
	signal data_next : std_logic_vector(3 downto 0);

begin

	process(clk)
	begin
		if rising_edge(clk) then
			data_current <= data_next;
		end if;
	end process;
	
	with update_pulse select data_next <=
		data_current(0) & data_current(3 downto 1) when '1',
		data_current when others;
		
	anode <= data_current;
		
	

end Behavioral;

